Integrated circuits (IC) manufactured today generally rely upon an elaborate system of metallized interconnects to couple the various devices which have been fabricated in the semiconductor substrate. The technology for forming these metallized interconnects is extremely sophisticated and well-understood by practitioners in the art.
Commonly, aluminum or some other metal is deposited and then patterned to form interconnect paths along the surface of the silicon substrate. In most processes, a dielectric or insulative layer is then deposited over this first metal (metal 1) layer; via openings are etched through the dielectric layer, and a second metalization layer is deposited. The second metal (metal 2) layer covers the dielectric layer and fills the via openings, thereby making electrical contact down to the metal 1 layer. The purpose of the dielectric layer, of course, is to act as an insulator between the metal 1 and metal 2 interconnects.
Most often, the intermetal dielectric layer comprises a chemical vapor deposition (CVD) of silicon dioxide which is normally formed to a thickness of approximately one micron. (Conventionally, the underlying metal 1 interconnect are also formed to a thickness of approximately one micron.) This silicon dioxide layer covers the metal 1 interconnects conformably such that the upper surface of the silicon dioxide layer is characterized by a series of non-planar steps which correspond in height and width to the underlying metal 1 lines.
These step-high variations in the upper surface of the interlayer dielectric have several undesirable features. First of all, a non-planar dielectric surface interferes with the optical resolution of subsequent photolithographic processing steps. This makes it extremely difficult to print high resolution lines. A second problem involves the step coverage of the metal 2 layer over the interlayer dielectric. If the step height is too large there is a serious danger that open circuits will be formed in the metal 2 layer.
To combat these problems, various techniques have been developed in an attempt to better planarize the upper surface of the interlayer dielectric. One approach employs abrasive polishing to remove the protruding steps along the upper surface of the dielectric. According to this method, the silicon substrate is placed face down on a table covered with a pad which has been coated with an abrasive material. Both the wafer and the table are then rotated relative to each other to remove the protruding portions. This abrasive polishing process continues until the upper surface of the dielectric layer is largely flattened.
One key factor to achieving and maintaining a high and stable polishing rate is pad conditioning. Pad conditioning is a technique whereby the pad surface is put into a proper state for subsequent polishing work. According to traditional methods, pad conditioning involves scraping the upper surface of the pad using a flat edged razer or knife-type blade. This removes the old polishing compound (i.e., slurry) from the polishing path and impregnates the surface of the pad with fresh slurry particles. In other words, the scraping process helps to clear the old or used abrasive material off of the pad surface. At the same time, a constant flow of fresh slurry across the pad surface helps to impregnate the pad with new abrasive particles. In the past, this technique has been most successful when applied to the class of polishing pads which comprise relatively soft, felt-like materials (such as the Rodel-500 pad manufactured by Rodel, Inc.).
However, when used with other, relatively hard pads (such as the IC60 pad manufactured by Rodel) the conventional razor or knife blade technique produces unsatisfactory results. When used with this class of pads, the polish rate for the straight-edge blade drops precipitously as more wafers are processed, thereby reducing manufacturability.
As will be seen, the present invention provides a method for conditioning the surface of a polishing pad while improving the polishing rate by a factor of 30-50% over that achieved using prior art techniques. Moreover, this relatively high polishing rate is held constant over a large number of wafers resulting in increased wafer-to-wafer uniformity. The present invention also extends the pad life well beyond that normally realized with past conditioning methods.